library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity output is
	
	port(
		enable: in std_logic;
		satisfied: in std_logic;
		led_1: out std_logic;
		led_2: out std_logic
	);
	
end output;

architecture output_behavior of output is

signal one: std_logic := '0';
signal two: std_logic := '0'; 

begin --architecture
	
process(enable)

begin --process
	
if enable = '1' then
	
	if satisfied = '1' then
		one <= '1';
		two <= '1';
	else
		one <= '1';
		two <= '0';
	end if;
end if;

end process;

led_1 <= one;
led_2 <= two;

end architecture output_behavior;
		
	
	


		